1. Field of the Invention
This invention relates to test logic in electronics and more particularly to synchronizing test logic.
2. Description of the Related Art
IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, also known as Joint Test Action Group (JTAG), provides a way to debug and test integrated circuits and boards. JTAG defines a test access port (TAP), which provides the capability to perform debug and testing. An exemplary JTAG test architecture 100 is shown in FIG. 1 and includes a TAP controller 101, and data and instruction registers 102 supplied by test data in (TDI) and supplying test data out (TDO). The TAP controller 101 receives a test clock (TCK), a control signal (test mode select (TMS)), and an optional reset signal TRST. The state machine associated with the TAP controller is shown in FIG. 2.